| Generation | Raw Bit Rate (per lane) | Encoding | Effective Bandwidth (per lane, x1) | | :--- | :--- | :--- | :--- | | Gen1 (2003) | 2.5 GT/s | 8b/10b | 250 MB/s | | Gen2 (2007) | 5.0 GT/s | 8b/10b | 500 MB/s | | Gen3 (2010) | 8.0 GT/s | 128b/130b | ~985 MB/s | | Gen4 (2017) | 16.0 GT/s | 128b/130b | ~1.97 GB/s | | Gen5 (2019) | 32.0 GT/s | 128b/130b | ~3.94 GB/s | | Gen6 (2022) | 64.0 GT/s | 1b/1b (PAM4 + FLIT) | ~7.88 GB/s |
In the landscape of modern computing, where central processing units (CPUs) operate at gigahertz frequencies and solid-state drives demand nanosecond latency, the ability to move data efficiently between components is as critical as processing power itself. At the heart of this data movement lies the Peripheral Component Interconnect Express (PCIe) Specification . More than just a physical slot on a motherboard, PCIe is a sophisticated, high-speed serial bus architecture that has become the universal interconnect for internal hardware. From graphics cards and NVMe storage to network adapters and AI accelerators, the PCIe specification dictates how the core components of a computer communicate, evolving continuously to keep pace with the relentless demands of modern workloads. From Parallel Buses to Serial Lanes To appreciate PCIe, one must understand the problem it solved. Its predecessors, including the original PCI and PCI-X, used a parallel bus architecture . Multiple devices shared a single, wide bus (32 or 64 bits) and communicated over a common clock signal. While conceptually simple, this approach faced severe physical limitations. As clock speeds increased, signals on parallel lines began to interfere with each other (a phenomenon known as crosstalk), and skew—where signals on different lines arrive at slightly different times—became impossible to manage. The parallel bus had hit a "speed wall." pci express specification
Furthermore, the specification has birthed derivative standards. builds on the PCIe physical and electrical layer to provide cache-coherent memory sharing between CPUs and accelerators, a critical feature for data-center AI and big-data workloads. Without PCIe as its foundation, CXL would not exist. Challenges and the Future The PCIe specification faces physical challenges as speeds increase. At Gen5 and Gen6, signal integrity becomes extremely sensitive to motherboard trace routing, connector quality, and even the material of the printed circuit board. Short trace lengths and low-loss materials are mandatory. Moreover, power consumption and heat dissipation at 64 GT/s are non-trivial concerns for mobile and data-center environments. | Generation | Raw Bit Rate (per lane)
GT/s = Giga-transfers per second; MB/s = Megabytes per second. From graphics cards and NVMe storage to network
